Electron Tube Nor Gate


The NOR gate is a circuit which produces an output signal only when there are no signals on any of the inputs. If you are short on time you only need to grasp that, in principle, triode electron tubes switch OFF with a negative grid voltage, and ON with a positive grid voltage.

The Ena.Computer is created from 550 of these NOR gates, and each one uses both triodes in the 6N3P glass tube.

5 volts on any input turns the first triode ON. A voltage dividing trimmer sits between the anode and -40 volts. Its output voltage is set to -2v which turns the second triode OFF and keeps the output LOW. On the other hand, if all inputs are 0v or below, the first triode is switched OFF, which increases its resistance, and anode voltage, raising the trimmer output voltage to a positive voltage, which switches ON the second triode, creating a current through the 51k load, making the output HIGH.

So it only has a HIGH output if, and only if, all inputs are LOW, which is the NOR gate function.

Component Values


I sourced the 6N3P Electron tubes mainly from the Russian Federation, but also from Slovakia, Poland, and Ukraine. They were produced by several Soviet block factories and differ in performance.

I wanted to mitigate the gain variations of the 6N3P electron tubes as simply as possible. All other considerations were secondary.

Normally all active components are almost identical and you can accurately calculate the optimum value for a circuit component. The selection of values for the Ena.Computer NOR Gate was different.

I calculated the component values and tested the results, but in many cases the theory did not accurately match the practice. So I built a test rig with two variable power supplies to test the stability of various component values. I chose several electron tubes from each source, ran the tests, and found a range of optimum values that worked for all the tubes. My final criteria was to select the lowest power standard values for the components. I then stress tested the whole thing again!

System Design


As the Ena.Computer is an original design I kept the number of sub circuits to an absolute minimum to reduce the inevitable screw ups. This page contains all the sub circuits.

Initially I tried various architectures with different types of gates, but they all became too intricate, and I failed to remember to “keep it simple, keep it clean”. Eventually I made a design just using NOR gates.

I modelled a tube NOR gate and I was able to test the design on a modern simulator, which just about worked, and so I built an electron tube test rig with 5 NOR gates, and to my amazement that also worked.

I recently discovered that a few incredibly important computers had designs based entirely on NOR gates. It goes to show that an electronics education could have halved the design time, and also filled this page with sophisticated technical prose.

Electron Tube Latch


An electronic latch is a 1 bit memory. In the Ena.Computer a simple Set and Reset [SR] latch remembers which oscillator should feed the clock.

If you are short on time, you only need to grasp that it takes a finite amount of time for a circuit to act. If an input changes state, then the output stays in its original condition for a short moment.

If all inputs are initially low, a [FAST] pulse sets the first NOR gate low, which sets the second NOR gate high, which then feeds back to the first NOR gate, keeping the first NOR gate output low. This will stay for a moment after the [FAST] pulse ends, keeping the [SPEED] output high, until a [SLOW] pulse resets the latch. The initial state is set by the order in which the tubes warm up. The first machine code usually sets the latch to [FAST], or you can press the [CLEAR] button on the console.

Enough, I hear you cry


If you are short on time, this is about it really, but please do look at the project management page.

It not only features my two lighthouses, but to further raise the hysteria, it also contains several split infinitives. Otherwise please keep reading!

Decoupling Capacitors, Optical RAM and a Nice Cup of Tea

They say you can never have too much decoupling, or was that chocolate?

Decoupling capacitors are extremely important, they provide a bypass path for transient currents which would otherwise cause voltage spikes on common power supply paths. Every Ena.Computer NOR gate has a pair of decoupling capacitors. A 10uF, for local energy storage, and a 100nF to provide the bypass route to ground.

In an attempt to create a memory with no moving parts I have experimented with photocells illuminated by lamps and leds as experimental NOR gates. A pair would be a simple SR latch memory cell. I built three, just to test the idea. The prototypes take over 120ms to switch, but do form a stable ring oscillator. I have yet to build a complete optical NOR memory system, but hopefully fibre optics will form the core.


The final form of the Ena.Computer also incorporates a bit7 carry forward register. The result is held and later used by the [ADDC] instruction, enabling 16, 32 and 64 bit maths. I have recently considered whether 128 bits might work using using the Page RAM.

Yes ridiculous, but it would give you plenty of time to make a nice cup of tea, or maybe have a three course lunch with a friend.


Electron Tube Register


Registers use over 400 electron tubes in the Ena.Computer. Each register consists of 8 D latches except the Instruction, and Rampage registers, which only have 4. All have a [CLEAR] to initially set the latch to a known state. They operate as conventional D latches, except that they are NOR instead of NAND, so the Load pulse is active Low. They input both data and NOTdata from 12 bit buses. and so do not require a NOT gate. All have a final active low enable to bus stage, which also conveniently acts as a zero substitute on the output from the X and Y registers to the ALU.

Electron Tube ALU

I designed the ALU to only generate four functions, [SUM], [XNOR], [NOT] and [INC]. A combination of two instructions can produce Subtract, Decrement, and XOR. Any more complexity seemed superfluous!

The 8 bit ALU in the Ena.Computer uses 72 electron tubes.

X and Y registers permanently feed the ALU with data, which the ROM microcode can substitute with a zero value.

Each ALU stage generates a Carry Out [COUT] which becomes the Carry In [CIN] for the next stage.

A [CSET] sets all ALU carries to 1, creating the bitwise XNOR function, The [CSET] is also used by the [NOT] instruction when, after storing the current accumulator value and also loading it in the Y register, the microcode substitutes zero as the X register output value and stores the [NOT] ALU value into the accumulator.

Electron Tube Switch


Each RAM page can support a different RAM type. The clock speed is switched by the software selecting an oscillator, so that different types of memory can coexist within a single program.

This circuit sometimes causes glitches with short double pulses on changeover, and is a problem. Better solutions would be to either use synchronised oscillators or to only switchover during an established oscillator state.

To help debug a program there are a set of console switches, which stop and pulse the oscillator feed to the clocks.

Hybrid Memory


Currently I am using a hybrid memory with electron tube address, clear, read & write NOR gates coupled to double reed relay memory cells plus a NVRAM.

My main design criteria for the Ena.Computer RAM was to mitigate problems caused by sticky change over relays. I've had a few catastrophic sticky relay events in the past, enough said. All other considerations were secondary. I wanted to use only normally open single pole reed relays, but for the few normally closed contacts I employ one side of a standard SPDT relay. To keep the load currents supplied by the 6N3P relay drivers down to around 10ma, the reed relays have 12v coils and the SPDT relays 24v. The reeds switch in under 2ms and so far only 2 relay memory cells have died.

Electron Tube Oscillator


The Ena.Computer has two oscillators, both are 3 NOR ring oscillators, each with 3 plugable capacitor delays. Links on the top of a 10 tube auxiliary board select the capacitors and the buffers square up the rounded outputs of the oscillators, and provide isolation from a change in load. Three polyester 470pfs result in a frequency of 11.3kHz, two gives 16.9kHz and one 33.8kHz.

The slow oscillator has three 1uf non polarized ceramic capacitors resulting in frequencies of 7Hz, 10Hz and 21Hz for the relay RAM.

In recent tests the oscillators have run from under 0.1Hz to almost 100kHz. Logic levels of the electron tube NOR gates are nominally 0v & 5v and the fan-out is about 25

Data Bus Zero Test


A key component of the Machine code is the [JUMPzero] instruction. If the accumulator value is zero the program branches. This circuit tests to see if the value of the lower 8 bits of the data bus is zero. The clock value used to to activate the last [JUMPzero] microcode is then disabled and the program branches to the operand address [ELSE] the program continues. [JUMPzero] can be achieved by several conditions, including identical or complimentary X & Y Register values or if either the sum or individual value of the two data registers is either 0 or -1.

The PONG program uses this instruction, it selectively branches the program to calculate the next location of the ball.

A New System Console and an Ambiguous Life Expectancy

The Final Form of the Ena.Computer has a totally rebuilt system console, which lifts open from the front. The top row now has 240 status monitoring leds identifying dead or faulty electron tubes.

There are 5 PSUs behind the console, each can take a 60 Amp short, The console now only switches 12v and 5v, all 240v is now direct to plugs.

I've moved GUI relays that I thought would never need to see the light of day, so I can now tap them for no good reason, and finally I've managed to reduce the high voltage potential on the PCBs right down to 80 volts, any lower and I'll need a PP3 battery. It's health and safety gone mad!

Ena.Computer has 16 single step instructions for data storage, data manipulation and program control.

The instructions are [LOADA], [LOADX], [LOADY], [STOREA], [ JUMPzero] a conditional jump if the Accumulator is zero, [GOTO], [INPUT] & set slow clock, [OUTPUT] & set fast clock, [ADD], [XNOR], [INC], [NOT], [ADDC] which is [ADD] plus carry in, [GUIW] the GUI relay RAM write, [GUIR] the GUI relay RAM read, and [RAMP] the RAM Page register value. Most of my programs exist in loops, but as a "17th [HALT] code” I annoy everyone by using two [GOTO]s in a loop. Not quite Python, but it works for me.

The finest 6N3P tubes were selected at manufacture for military use, with up to 5000 hours life expectancy and printed with an extra code (Russian 6Н3П-ЕВ). The rest were for domestic use, and with the ability to operate at over 200Mhz, the 6N3P was used in many 1960s Soviet VHF radio sets. The finest can source over 18ma and so can easily switch a reed relay. The basic quality tube has codes for a projected life span of either 1500 (6Н3П-Е) or only 500 hours (6Н3П). They have been held in post Soviet stores for 60 years, and some quality stamps may have been accidentally altered, so life expectancy may be questionable (both for the tubes and for me).



The Main Boards


I spent a lot of time designing the PCBs. I tried to make the boards both robust enough to handle the large currents and configurable enough to simplify the build.


The 8 main boards are 476mm x 393mm, each hold either 60 or 70 tubes, weigh just over 2Kg and are designed in 3 sections.

At the top are two 17mm wide heater supply tracks, which can conduct 25 amps whilst self heating about 5 degrees above ambient. The heater track pair are fed from the top screw terminals, via a quad 1mm cable from the 60 Amp power supplies. Pairs of 1mm tracks each supply 5 electron tubes with 1.75 Amps via an SMD fuse. There is a 0.2 voltage drop along this heater feed.


The central section of the main board processes a single bit of the data with electron tubes configured for 1 bit of the accumulator, and X and Y data registers, complement data, 1 bit of the ALU, program counter, memory address register, instruction register, plus single input, output and GUI read and write buffers. There are also double D latch clocks on boards #0 to #3 plus ROM address decoders and a further 5 NOR gates to process ROM microcodes. Boards #4 to #7 have empty clock sections.


The bottom section has the inter board connections and a ridiculous number of test points. A 280 way bus connects all the boards and each board is configured for its own needs. The data bit, compliment data, register load and enables to bus, input and output commands, ALU carry in and out, HV supplies, and all the other appropriate signals are connected by several small mezzanine boards which act as two dimensional jumpers..

Each electron tube board is mounted onto the 4mm acrylic wall panel using sixteen 3mm x 20mm offsets. The 190cm x 130cm wall panel is attached via three 2m x 30mm x 30mm aluminium box sections to the wall. The total wall load is about 31Kg and fortunately, the wall is made of brick.